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INTEGRATED CIRCUITS
DATA SHEET
74AHC1G07; 74AHCT1G07 Buffer with open-drain output
Product specification File under Integrated Circuits, IC06 2000 May 02
Philips Semiconductors
Product specification
Buffer with open-drain output
FEATURES * High noise immunity * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V * Low power dissipation * SOT353 package * Output capability standard (open drain). DESCRIPTION
74AHC1G07; 74AHCT1G07
The 74AHC1G/AHCT1G07 is a high-speed Si-gate CMOS device. The 74AHC1G/AHCT1G07 provides the non-inverting buffer. The output of the 74AHC1G/AHCT1G07 devices is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. For digital operation this device must have a pull-up resistor to establish a logic HIGH-level.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 3.0 ns. TYPICAL SYMBOL tPZL tPLZ CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. FUNCTION TABLE See note 1. INPUT inA L H Note 1. H = HIGH voltage level; L = LOW voltage level; Z = high impedance OFF-state. OUTPUT outY L Z PARAMETER propagation delay inA to outY propagation delay inA to outY input capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC1G CL = 15 pF; VCC = 5 V CL = 15 pF; VCC = 5 V 2.5 4.2 1.5 5.0 AHCT1G 2.8 3.9 1.5 6.5 ns ns pF pF UNIT
2000 May 02
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Philips Semiconductors
Product specification
Buffer with open-drain output
ORDERING AND PACKAGE INFORMATION PACKAGES TYPE NUMBER 74AHC1G07GW 74AHCT1G07GW PINNING SYMBOL n.c. inA GND outY VCC PIN 1 2 3 4 5 not connected data input ground (0 V) data output DC supply voltage DESCRIPTION TEMPERATURE RANGE -40 to +125 C PINS 5 5 PACKAGE SC-88A SC-88A MATERIAL plastic plastic
74AHC1G07; 74AHCT1G07
CODE SOT353 SOT353
MARKING AS CS
handbook, halfpage
n.c. 1 inA GND 2 3
MNA588
5 VCC
handbook, halfpage
07
4 outY
2
inA
outY
4
MNA589
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2000 May 02
3
Philips Semiconductors
Product specification
Buffer with open-drain output
74AHC1G07; 74AHCT1G07
handbook, halfpage handbook, halfpage
outY
inA
2
4
outY inA
MNA590
GND
MNA591
Fig.3 IEC logic symbol.
Fig.4 Logic diagram.
RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature input rise and fall times ratios (except for Schmitt-trigger inputs) active mode high-impedance mode see DC and AC characteristics per device VCC = 3.3 0.3 V VCC = 5 0.5 V CONDITIONS MIN. 2.0 0 0 0 -40 -40 - - TYP. 5.0 - - - +25 +25 - - MAX. 5.5 5.5 VCC 6.0 +85 +125 100 20 MIN. 4.5 0 0 0 -40 -40 - - TYP. 5.0 - - - +25 +25 - - MAX. 5.5 5.5 VCC 6.0 +85 +125 - 20 V V V V C C ns/V ns/V 74AHCT UNIT
tr, tf (t/f)
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Philips Semiconductors
Product specification
Buffer with open-drain output
74AHC1G07; 74AHCT1G07
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK VO IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 55 C the value of PD derates linearly with 2.5 mW/K. PARAMETER DC supply voltage input voltage DC input diode current DC output clamping diode current output voltage DC output sink current DC VCC or GND current storage temperature power dissipation per package for temperature range: -40 to +125 C; note 2 VI < -0.5 V; note 1 VO < -0.5 V; note 1 active mode; note 1 high-impedance mode; note 1 VO > -0.5 V CONDITIONS MIN. -0.5 -0.5 - - -0.5 -0.5 - - -65 - MAX. +7.0 +7.0 -20 20 V V mA mA UNIT
VCC + 0.5 V 7.0 25 75 +150 200 V mA mA C mW
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5
Philips Semiconductors
Product specification
Buffer with open-drain output
DC CHARACTERISTICS 74AHC1G family Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOL LOW-level output voltage VI = VIH or VIL; IO = 50 A VI = VIH or VIL; IO = 4 mA VI = VIH or VIL; IO = 8 mA II IOZ ICC CI input leakage current VI = VCC or GND 2.0 3.0 4.5 3.0 4.5 5.5 MIN. 1.5 2.1 3.85 - - - - - - - - - - - - - - - - - - 0 0 0 - - - - - 1.5 25 - - - 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 0.1 Tamb (C) -40 to +85 - - - 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 1.0 2.5 10 10
74AHC1G07; 74AHCT1G07
-40 to +125 - - - 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 2.0
UNIT
TYP. MAX. MIN. MAX. MIN. MAX. 1.5 2.1 3.85 - - - - - - - - - 1.5 2.1 3.85 - - - - - - - - - - - - V V V V V V V V V V V A
5.5 3-state output VI = VIH or VIL; OFF-state current VO = VCC or GND quiescent supply current input capacitance VI = VCC or GND; 5.5 IO = 0 -
0.25 - 1.0 10 - -
10.0 A 20 10 A pF
2000 May 02
6
Philips Semiconductors
Product specification
Buffer with open-drain output
74AHCT1G family Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output VI = VIH or VIL; voltage IO = 50 A VI = VIH or VIL; IO = 8 mA II IOZ input leakage current 3-state output OFF-state current VI = VCC or GND VCC (V) MIN. - - 0 - - - 25 - 0.8 0.1 0.36 0.1 Tamb (C)
74AHC1G07; 74AHCT1G07
-40 to +85 - 0.8 0.1 0.44 1.0 2.5
-40 to +125 UNIT - 0.8 0.1 0.55 2.0
TYP. MAX. MIN. MAX. MIN. MAX. 2.0 - - - - 2.0 - - - - - V V V V A
4.5 to 5.5 2.0 4.5 to 5.5 - 4.5 4.5 5.5 - - - -
VI = VIH or VIL; 5.5 VO = VCC or GND
0.25 -
10.0 A
ICC ICC
quiescent supply VI = VCC or GND; 5.5 current IO = 0 additional quiescent supply current per input pin input capacitance VI = 3.4 V; other inputs at VCC or GND; IO = 0
-
- -
1.0 1.35
- -
10 1.5
- -
20 1.5
A mA
4.5 to 5.5 -
CI
-
-
1.5
10
-
10
-
10
pF
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Philips Semiconductors
Product specification
Buffer with open-drain output
AC CHARACTERISTICS Type 74AHC1G07 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 3.0 to 3.6 V; note 1 tPZL tPLZ tPZL tPLZ propagation delay inA to outY propagation delay inA to outY see Figs 5 and 6 15 pF - - see Figs 5 and 6 50 pF - - see Figs 5 and 6 15 pF - - see Figs 5 and 6 50 pF - - 3.5 5.8 5.0 8.3 5.6 7.9 8.0 11.5 1.0 1.0 1.0 1.0 6.3 8.4 9.0 12.0 CL MIN. 25 Tamb (C) -40 to +85
74AHC1G07; 74AHCT1G07
-40 to +125
UNIT
TYP. MAX. MIN. MAX. MIN. MAX.
1.0 1.0 1.0 1.0
7.0 8.9 10.0 12.5
ns ns ns ns
VCC = 4.5 to 5.5 V; note 2 tPZL tPLZ tPZL tPLZ Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. Type 74AHCT1G07 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 1 tPZL tPLZ tPZL tPLZ Note 1. Typical values at VCC = 5.0 V. propagation delay inA to outY propagation delay inA to outY see Figs 5 and 6 15 pF - - see Figs 5 and 6 50 pF - - 2.8 3.9 4.0 5.5 4.6 5.6 6.5 8.0 1.0 1.0 1.0 1.0 5.3 6.1 7.5 8.5 1.0 1.0 1.0 1.0 5.6 6.6 8.0 9.0 ns ns ns ns CL MIN. 25 Tamb (C) -40 to +85 -40 to +125 UNIT propagation delay inA to outY propagation delay inA to outY 2.5 4.2 3.6 6.0 3.9 5.1 5.5 7.5 1.0 1.0 1.0 1.0 4.6 5.6 6.5 8.0 1.0 1.0 1.0 1.0 4.9 6.1 7.0 8.5 ns ns ns ns
TYP. MAX. MIN. MAX. MIN. MAX.
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Philips Semiconductors
Product specification
Buffer with open-drain output
AC WAVEFORMS
74AHC1G07; 74AHCT1G07
handbook, full pagewidth
VI inA input GND t PLZ VCC outY output VOL VOL + 0.3 V
MNA592
VM(1)
t PZL
VM(2)
FAMILY AHC1G AHCT1G
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM(1) INPUT 1.5 V
VM(2) OUTPUT 50% VCC
50% VCC 50% VCC
Fig.5 The input inA to output outY propagation delays.
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL
MNA232
VO
RL = 1000
VCC open GND
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH VCC
S1 open GND
Definitions for test circuit: CL = Load capacitance including jig and probe capacitance (see Chapter "AC characteristics"). RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator.
Fig.6 Load circuitry for switching times.
2000 May 02
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Philips Semiconductors
Product specification
Buffer with open-drain output
PACKAGE OUTLINE Plastic surface mounted package; 5 leads
74AHC1G07; 74AHCT1G07
SOT353
D
B
E
A
X
y
HE
vMA
5
4
Q
A
A1
1
e1 e
2
bp
3
wM B detail X Lp
c
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E (2) 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT353
REFERENCES IEC JEDEC EIAJ SC-88A
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
2000 May 02
10
Philips Semiconductors
Product specification
Buffer with open-drain output
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
74AHC1G07; 74AHCT1G07
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2000 May 02
11
Philips Semiconductors
Product specification
Buffer with open-drain output
Suitability of surface mount IC packages for wave and reflow soldering methods
74AHC1G07; 74AHCT1G07
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2000 May 02
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Philips Semiconductors
Product specification
Buffer with open-drain output
DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
74AHC1G07; 74AHCT1G07
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2000 May 02
13
Philips Semiconductors
Product specification
Buffer with open-drain output
NOTES
74AHC1G07; 74AHCT1G07
2000 May 02
14
Philips Semiconductors
Product specification
Buffer with open-drain output
NOTES
74AHC1G07; 74AHCT1G07
2000 May 02
15
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613507/01/pp16
Date of release: 2000
May 02
Document order number:
9397 750 07041

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